The present invention relates to integrated circuit (IC) devices, and in particular relates to voltage regulators for IC devices, such as non-volatile memory arrays, that require constant voltage levels over a wide range of processing and operating conditions.
FIG. 1 is a simplified schematic diagram showing a portion of a conventional memory device 100 that includes an array 110 of non-volatile memory cells 112 (one shown), a bit line control circuit 120, and a conventional voltage regulator 130. Other portions of conventional memory device 100 are omitted for brevity.
According to well-established techniques, the memory cells of array 110 are arranged in rows and columns, and each memory cell 112 is accessed during read, program, or erase operations by applying appropriate voltages to associated word and bit lines. For example, as indicated in FIG. 1, the gate terminal of each memory cell 112 is connected to an associated word line WL, and the drain and source terminals of memory cell 112 are connected to associated bit lines BL1 and BL2. Each memory cell of array 110 is addressed using a word line control circuit (not shown) and a bit line control circuit 120 that includes multiplexing circuits (YMUXes) 122 and 124. Specifically, YMUX 122 includes a series of pass transistors (not shown) that are controlled (turned on and off) by a first set of control signals to connect bit line BL1 to an appropriate voltage source. Similarly, YMUX 122 includes pass transistors that are controlled to connect bit line BL2 to ground during a read operation or to a sense amplifier.
During the operational lifetime of each nonvolatile memory cell 112, it is important that drain voltage Vdrain and gate voltage Vgate be constant over all temperature, system power supply (Vdd) and fabrication process variations (referred to herein as xe2x80x9cvariable conditionsxe2x80x9d). Variations of Vdrain produce threshold voltage (Vt) margin loss, which is the difference between the threshold voltage of a programmed cell versus the threshold voltage of an erased cell. When Vt margin loss occurs, the possibility of operational error increases.
Conventional voltage regulator 130 is provided in an attempt to maintain a constant Vdrain during read operations over the variable conditions. Voltage regulator 130 includes an operational amplifier 132, a PMOS pull-up transistor 134, a clamp transistor 136, and a voltage divider 138. Operational amplifier 132, PMOS transistor 134, and voltage divider 138 are connected to generate a reference voltage Vblr that controls the gate voltage of clamp transistor 136 in response to a band gap reference voltage Vbgref, which by definition is constant over the variable conditions and is applied to the inverting input terminal of operational amplifier 132. The output terminal of operation amplifier 132 is applied to the gate terminal of PMOS transistor 134, which has a first terminal connected to a first voltage source Vext1, thereby causing PMOS transistor 134 to generate reference voltage Vblr. Reference voltage Vblr is passed from the second (lower) terminal of PMOS transistor 134 to the gate terminal of clamp transistor 136 and to voltage divider 138. Voltage divider 138 includes a first resistor R1 connected between the second terminal of PMOS transistor 134 and the non-inverting input terminal of operational amplifier 132, and a second resistor R2 that is connected between resistor R1 and ground. Resistors R1 and R2 are selected to satisfy the equation: Vblr=Vbgref*(1+R2/R1). Accordingly, because band gap reference voltage Vbgref is constant over the variable conditions, reference voltage Vblr is also constant over the variable conditions. Clamp transistor 136, which is controlled by reference voltage Vblr, is connected between a second voltage source Vext2 and YMUX 122. Reference voltage Vblr clamps the source voltage of clamp transistor 136, and passes a reduced voltage (i.e., Vblrxe2x88x92Vgs) through YMUX 122 to the drain of memory cell 112.
A problem with voltage regulator 130 is that it does not account for resistance variations of pass transistors (not shown) utilized in YMUX 122 that are applied to the drain of memory cell 112. That is, regardless of the stability of reference voltage Vblr, the resistance of these pass transistors changes in response to variable operating conditions (e.g., temperature) and processing parameters, thereby resulting in potential Vt margin loss because the drain voltage Vdrain applied to memory cell 112 varies widely over the operational lifetime of memory device 100.
What is needed is voltage regulator for a memory array that compensates for the resistance variations generated in the multiplexing circuit used to access the memory cells of a memory array such that optimal voltage conditions are applied to the memory cells over all process, temperature, and voltage supply variations.
The present invention is directed to a memory device including a voltage regulator that compensates for resistance variations in the bit line control (multiplexing) circuit used to access the memory cells, thereby providing optimal voltage supply conditions during read operations over all variable conditions. This compensation is achieved by including in the feedback path of the voltage regulator an emulated multiplexing circuit having an identical resistance to that of the multiplexing circuit (or a multiple thereof). This emulated multiplexing circuit is fabricated using the same processing parameters as the multiplexing circuit, and includes the number of series-connected pass transistors that are utilized in the multiplexing circuit to access the memory cells, thereby causing the emulated multiplexing circuit to have an essentially identical resistance to that of the multiplexing circuit over all variable conditions. Accordingly, variations in the resistance of the multiplexing circuit caused by fabrication process variations, system voltage variations, or temperature variations are mirrored in emulated multiplexing circuit, thereby avoiding the Vt margin loss problems associated with conventional voltage regulators.
In accordance with a disclosed embodiment, a voltage regulator of the present invention is incorporated into a memory device including an array of 2-bit non-volatile memory cells. Each 2-bit memory cell has a first charge trapping region for storing a first bit that is read by applying a read voltage to a first terminal and connected the second terminal to ground, and a second charge trapping region for storing a second bit that is read by applying the read voltage to the second terminal and connecting the first terminal to ground. To facilitate this two-way access of each memory cell, a bit line control circuit includes a multi-level multiplexing circuit that selectively passes the read current in either direction through the memory cell. However, such 2-bit memory cells require a very precise drain voltage during read operations that cannot be too great (so as to inadvertently program the non-read bit) or too small (so that the non-read bit influences the read operation). Therefore, even relatively small changes in the variable conditions under which the multiplexing circuit are fabricated and/or operated can cause erroneous read operations. Accordingly, problems associated with the multiplexing circuit used to access 2-bit memory cells are particularly relevant to the present invention. However, the present invention may also be beneficially utilized in memory devices having single-bit memory cells, and also in any other IC devices requiring reliable voltage conditions at nodes accessed through multi-stage accessing circuits.
In the disclosed embodiment, the voltage regulator includes a differential (operational) amplifier, a pull-up transistor, and a feedback path (circuit) including an emulated multiplexing circuit having a resistance that is equal to that of the multiplexing circuit utilized to access a memory cell of the IC device. A first (e.g., inverting) input terminal of the differential amplifier is connected to receive a reference voltage (e.g., a band gap reference voltage), a second (e.g., non-inverting) input terminal of the differential amplifier is connected to receive a sample voltage from the feedback path, and an output terminal of the differential amplifier is connected to the gate terminal of the pull-up transistor. The pull-up transistor is connected between a first voltage source, and generates a reference voltage that controls a first clamp transistor connected between a second voltage supply and the multiplexing circuit. As mentioned above, the multiplexing circuit passes a read voltage from the first clamp transistor to the drain of a selected memory cell through a series of turned-on pass transistors. The reference voltage is also applied to a second clamp transistor of the feedback path, which also includes the emulated multiplexing circuit and a voltage divider. In accordance with an aspect of the present invention, the second clamp transistor is essentially identical to the first pass transistor (i.e., has the same size and is fabricated during the same process steps), and is connected between the second voltage source and the emulated multiplexing circuit. As mentioned above, the emulated multiplexing circuit includes a series of turned-on pass transistors that are essentially identical to the pass transistors of the multiplexing circuit (i.e., same number, same size, and fabricated during the same process steps). Therefore, the voltage passed through the emulated multiplexing circuit to the voltage divider is equal to the drain voltage passed through the multiplexing circuit to the memory cell. The voltage divider samples this emulated drain voltage, and passes the sampling to a second (e.g., non-inverting) terminal of the differential amplifier. In accordance with another aspect of the present invention, the voltage divider includes a first resistor R3 and a second resistor R4 the satisfy the equation: Vdemul=Vbgref*(1+R4/R3), where Vdemul is the emulated drain voltage, and Vbgref is the band gap reference voltage applied to the first input terminal of the differential amplifier. With the voltage divider constructed to satisfy this equation, the voltage divider of the present invention provides a constant drain voltage to the memory cells of the IC device over all variable conditions.
In accordance with yet another aspect of the present invention, the pull-up transistor is a PMOS transistor, and the voltage regulator includes a leaker circuit connected between the second terminal of the PMOS transistor and ground. The leaker circuit draws a constant current, and is provided to assure that the PMOS transistor remains in saturation. Further, the leaker circuit aids in the elimination of overshoots during stabilization of the reference voltage.